When a MOS Field Effect Transistor (FET) is composed in a bridge circuit, three power loss reductions are required.
The first power loss is on-state power loss. The on-state power loss is a power loss associated with current flowing through a channel of the MOSFET, and reduction of the on resistance of the MOSFET is required.
The second power loss is a switching power loss associated with turn-on switching. In order to reduce the switching power loss associated with the turn-on switching, it is required that a turn-on switching time period should be shortened by increasing a gate sensitivity of the MOSFET and reducing an amount of gate charge Qg needed for the turn-on switching.
The third power loss is a switching power loss associated with the turn-off switching, and is called “through loss”. In order to reduce the through loss, it is required that the turn-off switching time should be shortened by shortening Reverse Recovery Time trr of the MOSFET.
As shown in FIG. 11, a MOSFET of planar structure as a semiconductor device related to a conventional example includes: a high resistivity first base layer 12 of a first conductivity type; a drain layer 10 of the first conductivity type formed on the back side surface of the first base layer 12; a second base layer 16 of a second conductivity type formed on the surface of the first base layer 12; a source layer 18 of the first conductivity type formed on the surface of the second base layer 16; a gate insulating film 20 disposed on the surface of both the source layer 18 and the second base layer 16; a gate electrode 22 disposed on the gate insulating film 20; and an interlayer insulating film 24 disposed on the gate electrode 22. In FIG. 12, the illustration is omitted about a drain electrode disposed on the drain layer 10, and a source electrode disposed on both the source layer 18 and the second base layer 16.
FIG. 12 shows an example of a switching waveform of the semiconductor device related to the conventional example.
Although the MOSFET including the super junction MOS structure denotes higher performance in respect of both the switching power loss and the on-state power loss compared with the MOSFET of the conventional planar structure, the performance is poor in respect of the through loss.
That is, the super junction MOSFET includes a column layer of the second conductivity type formed in the first base layer 12 of the lower part of both the second base layer 16 and the source layer 18 by opposing the drain layer 10. Accordingly, the on resistance is reduced and the gate sensitivity increases, the amount of gate charge Qg needed for the turn-on switching is reduced, and thereby the turn-on switching time period can be shortened. On the other hand, since the column layer is included, a pn junction area increases, the reverse recovery time trr increases, and thereby the turn-off switching time is increased. Herein, the amount of gate charge Qg is defined as an amount of charge needed for a voltage VGS between the gate and the source in order to reach 10 V, for example.
Generally, a method of using diffusion of a heavy metal and a method of electron irradiation are known as technology for shortening the reverse recovery time trr. According to the above-mentioned methods, although the reverse recovery time trr can be shortened, since the controllability for forming a trap level is wrong, there is a problem that the leakage current between the drain and the source increases.
Also, in an insulated Gate Bipolar Transistor (IGBT), it is already proposed about a technology for forming locally a life-time controlled layer (for example, refer to Patent Literature 1).
Moreover, in the IGBT, it is already also disclosed about a technology for irradiating only a predetermined region with an electron ray by using a source electrode formed with aluminum as wiring and using as a mask of electron irradiation (for example, refer to Patent Literature 2).
Patent Literature 1: Japanese Patent Application Laying-Open Publication No. H10-242165 (FIG. 1, and Pages 3-4)
Patent Literature 2: Japanese Patent Application Laying-Open Publication. No. H10-270451 (FIG. 1, and Page 4)